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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT540 Octal buffer/line driver; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting FEATURES * Inverting outputs * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT540 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT540 The 74HC/HCT540 are octal inverting buffer/line drivers with 3-state outputs. The 3-state outputs are controlled by the output enable inputs OE1 and OE2. A HIGH on OEn causes the outputs to assume a high impedance OFF-state. The "540" is identical to the "541" but has inverting outputs. TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay An to Yn input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 9 3.5 39 HCT 11 3.5 44 ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting PIN DESCRIPTION PIN NO. 1, 19 2, 3, 4, 5, 6, 7, 8, 9 10 18, 17, 16, 15, 14, 13, 12, 11 20 SYMBOL OE1, OE2 A0 to A7 GND Y0 to Y7 VCC NAME AND FUNCTION 74HC/HCT540 output enable input (active LOW) data inputs ground (0 V) bus outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting FUNCTION TABLE INPUTS OE1 L L X H Notes OE2 L L H X 74HC/HCT540 OUTPUT An L H X X Yn H L Z Z 1. H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 max. 125 25 21 200 40 34 200 40 34 75 15 13 -40 to +125 min. max. 150 30 26 240 48 41 240 48 41 90 18 15 ns 74HC/HCT540 TEST CONDITIONS UNIT V CC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 min. typ. max. min. tPHL/ tPLH propagation delay An to Yn 3-state output enable time OE to Yn 3-state output disable time OE to Yn output transition time 30 11 9 52 19 15 61 22 18 14 5 4 100 20 17 160 32 27 160 32 27 60 12 10 tPZH/ tPZL ns Fig.7 tPHZ/ tPLZ ns Fig.7 tTHL/ tTLH ns Fig.6 December 1990 5 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting 74HC/HCT540 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE1 OE2 An UNIT LOAD COEFFICIENT 1.50 1.00 1.40 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPZH/ tPZL propagation delay An to Yn 3-state output enable time OE to Yn 3-state output disable time OE to Yn output transition time +25 -40 to +85 max. 30 44 -40 to +125 min. max. 36 53 ns ns 4.5 4.5 Fig.6 Fig.7 UNIT V CC WAVEFORMS (V) TEST CONDITIONS typ. max. min. 13 22 24 35 tPHZ/ tPLZ 23 35 44 53 ns 4.5 Fig.7 tTHL/ tTLH 5 12 15 18 ns 4.5 Fig.6 December 1990 6 Philips Semiconductors Product specification Octal buffer/line driver; 3-state; inverting AC WAVEFORMS 74HC/HCT540 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (An) to output (Yn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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